1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and particularly to a semiconductor device that is preferably applied to a multi-layer structure of field effect transistors having different conductivity types.
2. Related Art
Increasing attention is being paid to availability of a field effect transistor formed on an SOI substrate due to its advantages: easiness of element isolation, latch-up free, small source-to-drain coupling capacitance, and so on. In particular, a full depletion SOI transistor can achieve low power consumption and high-speed operation, and can easily be driven with a low voltage. Therefore, studies are strenuously progressed to operate an SOI transistor in the full depletion mode. As the SOI substrate, a separation-by-implanted-oxygen (SIMOX) wafer, a bonded wafer or the like is used as disclosed in e.g. JP-A-2002-299591 and JP-A-2000-124092, which are examples of the related-art documents.
In a complementary metal oxide semiconductor (CMOS) circuit such as a flip-flop, and an SRAM of which cells are each formed of six transistors, P-channel field effect transistors and N-channel field effect transistors are horizontally arranged adjacent to each other on the same two-dimensional plane.
When fabricating a SIMOX wafer, however, it is needed to ion-implant high concentration oxygen into a silicon wafer. When fabricating a bonded wafer, after two silicon wafers are bonded to each other, the surfaces of the silicon wafers need to be polished. Therefore, an SOI transistor problematically involves higher fabrication costs compared with a field effect transistor formed on a bulk semiconductor.
In addition, the ion-implantation and polishing involve a problem that variation in the film thickness of an SOI layer is large, and therefore it is difficult to stabilize characteristics of a field effect transistor when an SOI layer with a small thickness is formed in order to fabricate a full depletion SOI transistor.
Furthermore, if a plurality of transistors included in a flip-flop or SRAM are disposed on the same two-dimensional plane, the area required for forming the flip-flop or SRAM is large, which problematically precludes high-density integration. Moreover, another problem also arises that the length of interconnects required for coupling the plural transistors in the flip-flop or SRAM is large and therefore propagation delay is also large.